Verification Engineer
Ho Chi Minh City, Vietnam
Full-Time
Position Overview
As a Verification Engineer at GSME, you will play a critical role in ensuring the functional correctness and quality of our next‑generation SoC and ASIC designs. You’ll work closely with architecture, RTL, DFT, and physical design teams to verify complex digital blocks and subsystems using industry‑standard methodologies. This is an opportunity to join a fast‑growing US semiconductor company and contribute to high‑impact silicon programs built with advanced process technologies and state‑of‑the‑art EDA tools.
Key Responsibilities
Develop and maintain UVM based verification environments for block level and subsystem level testing.
Create test plans, define coverage goals, and ensure comprehensive functional verification.
Implement constrained random, directed, and coverage driven tests to validate RTL functionality.
Debug complex interactions between RTL, testbench components, and simulation models.
Analyze functional coverage, identify gaps, and drive closure.
Collaborate with RTL designers to review specifications, clarify requirements, and resolve issues.
Run simulations, regressions, and triage failures using industry standard tools.
Contribute to verification methodology improvements, automation, and best practices.
Qualifications
Required Skills & Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
7+ years of hands-on experience in ASIC/SoC functional verification
Hands on experience with SystemVerilog and UVM methodology.
Proficiency with simulation tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa.
Solid debugging skills using waveforms and simulation logs.
Familiarity with functional coverage, assertions, and constrained random verification.
Ability to read and understand RTL (Verilog/SystemVerilog).
Strong problem-solving skills and attention to detail.
Good communication skills and ability to work in cross functional teams.
Preferred Qualifications
Experience verifying complex SoCs, IP blocks, or subsystems.
Knowledge of UVM agents, scoreboards, monitors, and sequences.
Exposure to formal verification, linting, or CDC/RDC tools.
Familiarity with scripting languages (Python, Perl, Shell, Makefile) for automation.
Experience with advanced nodes and large‑scale verification environments.
Understanding of DFT concepts, synthesis flow, or physical design interactions.
Prior experience working with global teams or fast‑growing semiconductor companies.
What GSME Offers
Opportunities to work on cutting‑edge SoC and ASIC designs for next‑generation, high‑performance applications
A chance to join a fast‑growing US semiconductor company expanding its global engineering footprint
Access to state‑of‑the‑art EDA tools and advanced process technologies
Collaboration with cross‑functional teams across architecture, RTL, verification, DFT, synthesis, and physical design
Strong career growth through exposure to complex design challenges, large‑scale SoCs, and advanced technology nodes
Competitive compensation and clear advancement opportunities in a rapidly expanding Vietnam design center
A culture that values innovation, technical excellence, and continuous learning, supported by mentorship from experienced global teams