SOC - Physical Implementation (PI, PD, PV), Staff/ Sr.Staff Engineer
Ho Chi Minh City, Vietnam
Full Time
Position Overview
We are looking for an engineer to own the physical implementation of hierarchical blocks, block tops, or full chip tops. You will work closely with RTL designers, DFT engineers, and customers to deliver chips that meet their power, performance, and area (PPA) targets, and you will drive issues to resolution across teams.
Physical Implementation (PI): Review design architecture, power intent, and clock specs, and shape power, placement, and timing constraints. Run logical and physical synthesis, analyze and improve PPA, and own quality checks (LDRC, VCLP, GCA, LEC). Run MCMM STA, fix DRV, setup, hold, and crosstalk issues, execute timing ECOs, and lead timing sign-off. Partner with DFT and PnR engineers on SDC, timing debug, the HPDF implementation plan, and synthesis QoR.
Physical Design (PD): Work with the customer and package and interposer teams to define package type, chip size, and bump map. Design the IO ring and ESD network, implement hard IP, and plan the floorplan, clock distribution, HPDF, power domains, and PG-mesh. Run block or top-level PnR, improve PPA, and complete physical verification (DRC, LVS) and reliability checks (EM, IR-drop).
Key Responsibilities
Take ownership of physical implementation for hierarchical block, block top, or chip top.
For Physical Implementation engineers (PI):
Investigate design architecture, power intent, clock spec, and work closely with the customer or RTL-designers to make, change, or improve power, placement, timing constraints.
Run synthesis flow (logical + physical) and perform PPA analysis and improvement.
Perform all quality checks (LDRC, VCLP, GCA, LEC); proactively drive issue resolution with RTL, DFT and PD teams.
Perform MCMM STA, analyze and fix DRV/ Setup-Hold/ X-talk/ and other timing related items, execute Timing-ECO and lead Timing sign-off.
Collaborate closely with DFT engineers to make and refine SDC as well as to debug timing issues.
Collaborate closely with PnR engineers to make HPDF implementation plan, improve Synthesis QoR, update timing constraints, and realize the targeted PPA.
For Physical Design engineers (PD):
Work closely with the customer and PKG/ Interposer team to define PKG type, chip size, Bump map…
Design IO ring and ESD network, implement hard-IP physical implementation
Make chip floorplan, Clock distribution and HPDF implementation plan, and plans for Power domain and PG-mesh implementation.
Perform block or top level PnR and PPA improvement
Work closely with Synthesis/ DFT/ STA team for placement and timing constraints, timing ECO, power optimization and design improvement to meet sign-of conditions.
Perform physical verification (DRC, LVS), and reliability checks (EM, IR-DROP)
Provide informal mentorship to junior engineers;
Qualifications
YoE:
Staff: 6+ years of experience
Sr.Staff: 9+ years of experience
Strong hands-on experience in ASIC/SoC Implementation, from RTL to GDS, including Chip planning, IO/IP integration, Power design implementation, Synthesis, PnR, PV, EM-IR, STA and Timing ECO.
Strong knowledge of SoC/ASIC architectures (CPU, BUS/Interconnect, Memory hierarchy, Clock/Reset and Data transfer mechanisms), solid understanding of RTL synthesis and RTL-to-Gate implementation, with ability to analyze design architecture and recommend RTL/micro-architecture optimization for better PPA.
Experience with hand-off quality checks (LDRC, VCLP, GCA, LEC) and ability to debug issues independently.
Deep knowledge of SDC constraint, STA/ Timing ECO methodologies, and PPA trade-offs for Timing closure.
Good knowledge of PKG types, interposer/ bump/ RDL design, hands-on experience in IO/ IP integration, and implementation of ESD protection network.
Strong knowledge of power reduction methods, power intents, and low power design; Rich hands-on experience in Power domain and PG network implementation
Good hands-on experience on CTS and Clock Tree implementation; Strong knowledge of PPA/timing optimization techniques across the PnR flow.
Proficiency with PnR tools and good ability to effectively control the tools to improve timing QoR and achieve overall PPA.
Proficiency in Physical Verification flow and reliability checks, including DRC, LVS, EM, IRDROP.
Strong scripting skills (TCL, Python, Perl) for flow-automation and data analysis is an advance.
Strong analytical, debugging, and communication skills; ability to work effectively with global teams.