SoC - Physical Implementation, Senior Engineer
Ho Chi Minh - VN, Muscat - OM & Hsinchu - TW
Full Time
Position Overview
The SOC - Physical Implementation Senior Engineer is responsible for contributing to selected RTL-to-GDS activities for complex SoC/ASIC designs, with a focus on hand-off quality checks, SDC constraint development, synthesis with and without physical awareness, Static Timing Analysis (STA), timing ECO implementation, and power analysis. This role works closely with RTL, Physical Design, DFT, Verification, and customer teams to support design convergence, sign-off readiness, and successful project delivery. This role offers the opportunity to work on cutting edge silicon in a fast growing US semiconductor company and contribute to high impact SoC programs.
Key Responsibilities
Perform design hand-off checks including LDRC, VCLP, GCA, LEC, and other quality checks to ensure clean transition between RTL, synthesis, and physical implementation stages.
Develop, review, and maintain SDC constraints for block-level or assigned implementation scope, timing analysis, and sign-off support.
Run synthesis flows with and without physical awareness, analyze reports, optimize QoR, and support area, timing, and power targets within the assigned scope.
Perform Static Timing Analysis (STA) across modes and corners, including setup/hold analysis, SI/crosstalk impact, noise-related timing effects, timing closure support, and timing ECO generation for assigned blocks or modules.
Conduct power analysis and support low-power implementation checks to improve power quality and identify potential issues early in the design flow.
Collaborate closely with Physical Design engineers, especially during placement and Clock Tree Synthesis (CTS), to align constraints, timing intent, QoR targets, and implementation feedback for assigned blocks or modules.
Collaborate closely with DFT engineers for DFT insertion flow in synthesis and PnR stage.
Contribute to methodology improvement, flow automation, checklist development, and best-practice sharing for SoC Physical Implementation projects.
Qualifications
3 to 6 years of relevant experience in ASIC/SoC Physical Implementation, synthesis, timing analysis, or RTL-to-signoff design flows.
Hands-on experience with block-level or assigned-scope implementation activities.
Strong knowledge of SDC constraint creation, synthesis flows, Static Timing Analysis (STA), timing closure, and timing ECO generation.
Experience with synthesis and timing sign-off tools such as Synopsys Design Compiler/Fusion Compiler, PrimeTime, Cadence Genus/Tempus, or equivalent EDA tools.
Experience with hand-off and implementation quality checks such as LDRC, VCLP, GCA, LEC, and related design validation flows.
Understanding of power analysis, low-power design concepts, and power-aware implementation or verification flows is preferred.
Good understanding of ASIC/SoC design methodology, RTL-to-GDS flow, timing closure, PPA trade-offs, and cross-functional design dependencies.
Scripting experience with TCL, Perl, Python, or similar languages for flow automation, report analysis, and debug support.
Good analytical, debugging, problem-solving, and communication skills with the ability to work in global customer projects.