SoC - Physical Design, Staff Engineer
Ho Chi Minh - VN, Muscat - OM & Hsinchu - TW
Full Time
Position Overview
The SOC Physical Design Staff Engineer owns medium to large partitions, drives timing/EMIR/PV closure, and ensures robust implementation quality across multiple blocks. This role provides technical guidance to junior engineers and influences flow improvements within the PD team. This role offers the opportunity to work on cutting edge silicon in a fast growing US semiconductor company and contribute to high impact SoC programs.
Key Responsibilities
Lead floorplan, placement, CTS, routing for large blocks.
Drive timing closure, SI/crosstalk analysis, ECO strategy.
Lead IR/EM closure across partitions.
Ensure DRC/LVS clean results; debug complex PV issues.
Work with synthesis/STA teams to ensure timing intent consistency.
Collaborate with RTL, DFT, STA, and full-chip teams.
Improve scripts and PD methodologies.
Guide junior/senior engineers on PnR, STA, EMIR, PV.
Qualifications
6–9 years of experience in ASIC/SoC Physical Design with ownership of large blocks or partitions.
Deep expertise in PnR implementation: hierarchical floorplanning, advanced placement/CTS/routing strategies.
Strong proficiency in timing convergence, including SI/crosstalk analysis and complex ECO strategies.
Solid experience driving EMIR closure across medium-to-large partitions.
Strong capability in PV signoff, including debugging complex DRC/LVS issues and ensuring clean signoff.
Good understanding of full-chip integration, hierarchical flows, and cross-block dependencies.
Experience collaborating with RTL, STA, DFT, and full-chip teams to align constraints and timing intent.
Strong scripting/automation skills for improving PD flows and methodologies.
Ability to mentor junior engineers and review their implementation/debug work.
Strong communication skills for global team collaboration and customer interaction.