SoC - Physical Design, Senior Engineer
Ho Chi Minh - VN, Hsinchu - TW & Muscat - OM
Full Time
Position Overview
The SOC Physical Design Senior Engineer executes block‑level PnR, timing closure, EMIR checks, and physical verification for assigned SoC/ASIC partitions. This role focuses on hands‑on implementation, report analysis, and issue debugging while collaborating with RTL, STA, and DFT teams. This role offers the opportunity to work on cutting edge silicon in a fast growing US semiconductor company and contribute to high impact SoC programs.
Key Responsibilities
Perform Floorplan, placement, CTS, routing, and optimization for assigned blocks.
Run STA, debug violations, implement ECOs.
EMIR analysis — Perform IR drop and EM checks; fix local issues.
PV execution — Run DRC/LVS, fix violations, support signoff closure.
Power optimization — Identify hotspots and collaborate on fixes.
Cross-team collaboration — Work with RTL, STA, DFT teams to resolve issues.
Write scripts for PnR, STA, EMIR, PV flows.
Qualifications
3–6 years of hands-on experience in ASIC/SoC Physical Design (PnR, STA, EMIR, PV).
Strong experience with block-level PnR: floorplanning, placement, CTS, routing, and optimization.
Solid understanding of timing analysis, SI/crosstalk basics, and timing ECO implementation.
Practical experience running EMIR (IR drop, EM) checks and applying local fixes.
Hands-on experience with PV (DRC/LVS) and ability to debug common violations.
Familiarity with power optimization techniques (multi-Vt, clock gating, congestion/power hotspot fixes).
Experience with industry tools: Synopsys ICC2/Fusion Compiler, Cadence Innovus, PrimeTime, Voltus/RedHawk, Calibre.
Scripting skills in TCL, Python, or Perl for automation and report processing.
Good problem-solving, debugging, and communication skills; ability to work with cross-functional teams.