Design, build, and optimize system level emulation and FPGA prototyping platforms capable of handling designs from IP modules to large multi-billion-gate SoCs. 

Own bring-up, debug, and optimization of system level design models onto commercial emulation systems and FPGA prototyping systems.

Develop and implement methodologies for IP-level, SoC-level, and System-level prototyping flows, including:

• RTL synthesis, partitioning & multi-FPGA mapping

• High-speed interface bring-up in emulation or prototyping environment

• Clock modeling, clock domain crossing, timing closure

• Emulation/FPGA specific modifications

• Debug instrumentation & transaction-level visibility

Drive adoption of advanced system-level pre-silicon validation use cases with emulation and prototyping including early software/firmware development and co-verification, power estimation and optimization, performance characterization, etc.

Establish efficient flows for design iterations --- from IP validation to full-chip SoC tape-out readiness.

Perform complex debug of hardware/software issues using advanced tools (Verdi, DVE, Vivado Hardware Manager, SignalTap, transaction viewers, JTAG/trace debuggers). · Collaborate with various customer RTL design/verification/software teams to resolve design issues and performance challenges.

Mentor mid-level and senior engineers on technical topics and best practices; contribute to team technical direction.

Evaluate new tools, platforms, and technologies to improve platform capabilities and turnaround time.

Support silicon bring-up by assisting with transition of emulation/prototyping environments to lab hardware and initial silicon validation.

Participate in vendor technical engagements to address platform needs and optimize tool usage.