RTL Design Engineer - SoC
Ho Chi Minh City, Vietnam
Full-Time
Position Overview
As an RTL Design Engineer at GSME, you will be responsible for translating SoC architecture into high‑quality, synthesizable RTL. You will work closely with architects, verification engineers, and physical design teams to deliver high‑performance, low‑power digital designs that meet aggressive product requirements. This role offers the opportunity to contribute to advanced SoC programs within a fast‑growing US semiconductor company using state‑of‑the‑art tools and methodologies.
Key Responsibilities
Translate SoC architecture specifications into clean, synthesizable RTL using Verilog/SystemVerilog
Develop, integrate, and maintain IP blocks within the SoC design
Optimize RTL for timing, area, and power efficiency
Collaborate with verification teams to ensure functional correctness and achieve coverage goals
Support synthesis, linting, CDC/RDC checks, and STA during design handoff
Debug RTL issues and provide fixes in collaboration with cross‑functional teams
Document design specifications, maintain coding standards, and contribute to design reviews
Qualifications
Required Skills & Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
Strong proficiency in Verilog/SystemVerilog; VHDL knowledge is a plus
Solid understanding of digital design fundamentals: FSMs, pipelines, clock domains, resets, datapaths
7+ years of experience with synthesis tools such as Synopsys Design Compiler or Cadence Genus
Familiarity with linting, CDC/RDC checks, and basic static timing analysis (STA)
Knowledge of SoC bus protocols such as AMBA AXI/AHB/APB
Strong debugging skills and ability to work effectively in a collaborative, cross‑functional environment
Preferred Qualifications
Experience with low‑power design techniques (clock gating, power domains, UPF)
Exposure to UVM‑based verification environments
Familiarity with DFT concepts (scan, BIST)
Hands‑on experience with EDA tools from Synopsys, Cadence, or Mentor
Experience contributing to large‑scale SoC or multi‑IP integration projects
What GSME Offers
Opportunities to work on cutting‑edge SoC and ASIC designs for next‑generation, high‑performance applications
A chance to join a fast‑growing US semiconductor company expanding its global engineering footprint
Access to state‑of‑the‑art EDA tools and advanced process technologies
Collaboration with cross‑functional teams across architecture, RTL, verification, DFT, synthesis, and physical design
Strong career growth through exposure to complex design challenges, large‑scale SoCs, and advanced technology nodes
Competitive compensation and clear advancement opportunities in a rapidly expanding Vietnam design center
A culture that values innovation, technical excellence, and continuous learning, supported by mentorship from experienced global teams