Physical Design Engineer - Advanced Nodes (SoC)
Ho Chi Minh City, Vietnam
Full-Time
Position Overview
As a Physical Design Engineer at GSME, you will be responsible for implementing complex SoC designs at advanced technology nodes such as 7nm, 5nm, and 3nm. Physical Design is one of our most critical hiring needs as we expand next‑generation silicon programs. You will drive the backend flow from synthesis through tape‑out, ensuring that designs meet aggressive performance, power, and area (PPA) targets while adhering to foundry rules and manufacturability requirements. This role offers the opportunity to work on cutting‑edge silicon in a fast‑growing US semiconductor company and contribute to high‑impact SoC programs.
Key Responsibilities
Execute RTL‑to‑GDSII implementation, including synthesis, floor planning, placement, clock tree synthesis (CTS), routing, and timing closure.
Optimize designs for power, performance, and area (PPA) at advanced process nodes.
Perform static timing analysis (STA), signal integrity checks, IR‑drop analysis, and electromigration (EM) verification.
Ensure full DRC (Design Rule Check) and LVS (Layout vs. Schematic) compliance for tape‑out.
Collaborate closely with RTL, verification, DFT, and architecture teams to resolve timing, congestion, and power issues.
Drive ECO cycles to address late‑stage design changes and improve design quality.
Work directly with foundries to resolve process‑specific challenges and ensure manufacturability and yield readiness.
Contribute to methodology improvements, automation, and best practices for advanced‑node physical design.
Qualifications
Required Skills & Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
7+ years of hands‑on experience in physical design for complex ASIC/SoC projects.
Strong expertise with industry‑standard EDA tools: Cadence Innovus, Synopsys ICC2, PrimeTime, RedHawk, Voltus, or equivalent.
Solid understanding of advanced‑node challenges, including double patterning, FinFET device behavior, and EUV lithography constraints.
Proven experience with clock tree design, power grid planning, floorplanning, and hierarchical design flows.
Knowledge of low‑power design techniques such as multi‑voltage domains, UPF, power gating, and retention strategies.
Familiarity with DFT insertion, scan chain planning, and physical‑aware synthesis.
Strong debugging skills in timing, power, congestion, and signal integrity.
Ability to collaborate effectively with cross‑functional engineering teams.
Preferred Qualifications
Hands‑on experience with 7nm, 5nm, or 3nm process technologies.
Exposure to chip‑level integration, hierarchical P&R, and large‑scale SoC assembly.
Experience with automation or machine learning techniques for design optimization.
Background working on multi‑billion‑transistor SoCs or high‑performance compute designs.
Familiarity with reliability analysis, thermal modeling, or advanced sign‑off methodologies.
What GSME Offers
Opportunities to work on cutting‑edge SoC and ASIC designs for next‑generation, high‑performance applications
A chance to join a fast‑growing US semiconductor company expanding its global engineering footprint
Access to state‑of‑the‑art EDA tools and advanced process technologies
Collaboration with cross‑functional teams across architecture, RTL, verification, DFT, synthesis, and physical design
Strong career growth through exposure to complex design challenges, large‑scale SoCs, and advanced technology nodes
Competitive compensation and clear advancement opportunities in a rapidly expanding Vietnam design center
A culture that values innovation, technical excellence, and continuous learning, supported by mentorship from experienced global teams