DFT Engineer
Ho Chi Minh City, Vietnam
Full-Time
Position Overview
As a DFT Engineer at GSME, you will be responsible for implementing and validating the test architecture that ensures our advanced SoCs achieve high test coverage, manufacturability, and first‑silicon success. You will work closely with RTL, verification, synthesis, and physical design teams to insert scan, BIST, and test compression logic, generate ATPG patterns, and support silicon bring‑up.
Key Responsibilities
Develop and implement DFT architecture, including scan insertion, test compression, MBIST/LBIST, and boundary scan
Insert and validate scan chains, test points, and BIST logic at RTL or gate level
Define test modes, test clocks, and constraints for synthesis and physical design
Generate ATPG patterns, analyze fault coverage, and optimize for test quality and pattern count
Collaborate with RTL teams to ensure design testability and resolve DFT‑related issues
Work with physical design teams on scan chain reordering, test CTS, and timing closure in test modes
Support gate‑level simulations, test vector validation, and silicon bring‑up activities
Ensure DFT logic meets timing, area, and power requirements across all corners
Contribute to methodology improvements, automation, and best practices for DFT flows
Qualifications
Required Skills & Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
7+ years of hands‑on experience in DFT for ASIC/SoC designs
Strong experience with scan insertion, ATPG, MBIST/LBIST, and test compression
Proficiency with DFT and ATPG tools (Synopsys DFTMAX/TetraMAX, Cadence Modus, Mentor Tessent)
Solid understanding of digital design fundamentals and RTL testability requirements
Familiarity with synthesis flows, timing constraints, and physical design interactions
Experience with gate‑level simulation and debugging test‑mode timing issues
Strong analytical and problem‑solving skills, with the ability to work across cross‑functional teams
Preferred Qualifications
Experience with advanced nodes (7nm, 5nm, 3nm) and large‑scale SoCs
Knowledge of JTAG, IEEE 1500, boundary scan, and hierarchical DFT
Familiarity with low‑power test strategies (power‑aware ATPG, multi‑domain test modes)
Experience with automation using Python, Perl, or Tcl
Background supporting silicon bring‑up and production test
What GSME Offers
Opportunities to work on cutting‑edge SoC and ASIC designs for next‑generation, high‑performance applications
A chance to join a fast‑growing US semiconductor company expanding its global engineering footprint
Access to state‑of‑the‑art EDA tools and advanced process technologies
Collaboration with cross‑functional teams across architecture, RTL, verification, DFT, synthesis, and physical design
Strong career growth through exposure to complex design challenges, large‑scale SoCs, and advanced technology nodes
Competitive compensation and clear advancement opportunities in a rapidly expanding Vietnam design center
A culture that values innovation, technical excellence, and continuous learning, supported by mentorship from experienced global teams