DFT Engineer (All Levels)
Ho Chi Minh City, Vietnam – Da Nang city, Vietnam
A full-time position
Position Overview
The DFT Engineer will be responsible for architecting, implementing, validating, and optimizing Design-for-Test solutions for complex ASIC and SoC designs. This role involves working closely with RTL Design, Verification, Physical Design, Product Engineering, and Silicon Validation teams to ensure robust testability, high manufacturing yield, and successful product deployment.
We are seeking hands-on engineers with experience in Scan, ATPG, MBIST, LBIST, Boundary Scan, and silicon debug who are passionate about solving challenging problems in advanced semiconductor development.
Key Responsibilities
• Develop and implement Design-for-Test (DFT) architectures including Scan, Test Compression, MBIST, LBIST, and Boundary Scan solutions.
• Perform scan insertion, DFT validation, and test-mode integration at RTL and gate levels.
• Generate and debug ATPG patterns to achieve target fault coverage while optimizing pattern count and test costs.
• Define and validate DFT constraints, test clocks, test modes, and implementation requirements.
• Collaborate with RTL, Verification, and Physical Design teams to improve design testability and resolve DFT-related issues.
• Support scan chain planning, timing closure in test modes, and physical implementation of DFT structures.
• Perform gate-level simulation, test vector validation, and silicon bring-up debugging activities.
• Analyze test coverage, diagnose coverage gaps, and drive improvements in test quality and manufacturing readiness.
• Develop scripts and automation for DFT flows using Python, Perl, Shell, or Tcl.
• Contribute to methodology development and best practices across DFT implementation and verification flows.
Qualifications
1. Bachelor’s or master’s degree in electrical engineering, Computer Engineering, Electronics Engineering, or related field.
2. 5+ years of hands-on DFT experience for ASIC/SoC designs. (8+ years if targeting Senior level).
3. Strong experience with Scan, ATPG, MBIST, LBIST, Boundary Scan, and simulation/debug flows.
4. Proficiency with Synopsys TestMAX, Cadence Modus, or Siemens Tessent tool suites.
5. Strong understanding of digital design, RTL development, synthesis, timing
constraints, and physical design interactions.
6. Experience with gate-level simulation and test-mode debugging.
7. Strong analytical, debugging, and problem-solving skills.
8. Effective communication skills and ability to work within cross-functional engineering teams.
Preferred Skills & Experience
1. Experience with advanced technology nodes (7nm, 5nm, 3nm or below).
2. Knowledge of IEEE 1149.1 (JTAG), IEEE 1500, IEEE 1687, IEEE 1838, hierarchical DFT, and boundary scan architectures.
3. Experience with IP test patterns bring up for LPDDR, PCIE,
4. Familiarity with low-power DFT and power-aware ATPG methodologies.
5. Experience with Python, Perl, Shell, or Tcl scripting for automation.
6. Experience supporting silicon bring-up, characterization, and production test.