Chip Architect
Ho Chi Minh City, Vietnam
Full-Time
Position Overview
As a Chip Architect at GSME, you will define the architectural foundation of next‑generation SoCs used in high‑performance, low‑power applications. You will translate product requirements into system‑level specifications, drive architectural decisions, and guide RTL, verification, DFT, and physical design teams throughout the development cycle. This is a senior, high‑impact role within a fast‑growing US semiconductor company, offering the opportunity to shape silicon strategy, influence design methodology, and contribute to advanced technology‑node products.
Key Responsibilities
Define chip‑level architecture, including compute subsystems, memory hierarchy, interconnects, clocking, and power domains.
Translate product requirements into detailed architecture specifications, block diagrams, and design guidelines.
Evaluate performance, power, and area trade‑offs using modeling, simulation, and architectural exploration tools.
Work closely with RTL teams to ensure architectural intent is implemented accurately and efficiently.
Collaborate with verification teams to define test strategies, corner cases, and architectural coverage requirements.
Partner with physical design teams to ensure architecture aligns with timing, floor planning, and power constraints.
Drive system‑level integration, ensuring seamless interaction between IP blocks, subsystems, and SoC infrastructure.
Lead technical reviews, provide guidance on micro‑architecture decisions, and mentor engineering teams.
Stay current with industry trends, emerging architectures, and advanced process technologies to influence future product direction.
Qualifications
Required Skills & Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
7+ years of experience in SoC or ASIC design, with at least several years in architecture or micro‑architecture roles
Deep understanding of digital design fundamentals, SoC architecture, memory systems, and interconnect protocols
Strong experience with performance modeling, architectural simulation, or system‑level analysis
Solid understanding of RTL design, verification methodologies, and physical design constraints
Familiarity with low‑power architecture techniques (power domains, clock gating, DVFS, retention)
Knowledge of SoC bus and interconnect standards (AMBA AXI/ACE, NoC fabrics, cache coherency)
Strong analytical, problem‑solving, and communication skills
Ability to lead technical discussions and collaborate across global, cross‑functional teams
Preferred Qualifications
Experience architecting SoCs at advanced nodes (7nm, 5nm, 3nm)
Background in high‑performance compute, AI/ML accelerators, networking, or multimedia subsystems
Familiarity with security architectures, virtualization, or system‑level power management
Experience with architectural modeling tools (SystemC, C++, Python‑based modeling frameworks)
Prior involvement in multi‑billion‑transistor SoCs or large‑scale integration projects
Experience influencing product roadmaps or leading architecture teams
What GSME Offers
Opportunities to work on cutting‑edge SoC and ASIC designs for next‑generation, high‑performance applications
A chance to join a fast‑growing US semiconductor company expanding its global engineering footprint
Access to state‑of‑the‑art EDA tools and advanced process technologies
Collaboration with cross‑functional teams across architecture, RTL, verification, DFT, synthesis, and physical design
Strong career growth through exposure to complex design challenges, large‑scale SoCs, and advanced technology nodes
Competitive compensation and clear advancement opportunities in a rapidly expanding Vietnam design center
A culture that values innovation, technical excellence, and continuous learning, supported by mentorship from experienced global teams