Advanced IC Package Engineer
Ho Chi Minh - VN, Da Nang - VN, Muscat - OM, Hsinchu- TW, San Jose - US
Full Time
Competitive Compensation
Position Overview
We are seeking a motivated Advanced IC Package Engineer to join our Advanced Package Design team. This role offers hands on experience with real world semiconductor and package design, working directly on advanced packaging concepts including 2.5D/3D packaging, interposers, and modern package design methodologies. The ideal candidate brings strong layout experience with multi layer MLO/RDL and ceramic substrates, a solid grasp of signal and power integrity fundamentals, and a drive to grow within the global semiconductor industry under close mentorship.
Key Responsibilities
Support layout of multi layer MLO/RDL and ceramic substrate packages.
Work on multi layer stackups involving both core and coreless packages, gaining hands on exposure to advanced packaging concepts like 2.5D/3D packaging, interposers, and modern package design methodologies.
Apply impedance control principles, manage return paths, and minimize inductance loops in package layout.
Contribute to signal integrity (SI) and power integrity (PI) aware routing, including SERDES, DDR, and HSIO (Gen3/4/5/6) where applicable.
Collaborate with thermal, mechanical, electrical, reliability, and component teams to align package design with cross disciplinary requirements.
Stay aware of manufacturing processes and materials relevant to advanced packaging.
Gain experience used across the global semiconductor industry, with clear mentorship from senior engineers and exposure to top tier and startup semiconductor companies.
Qualifications
Bachelor's degree in Electrical Engineering, Mechanical Engineering, Industrial Engineering, Applied Physics, Physics, or a related field, with strong fundamentals in Electrical/Electronic Engineering, Physics, or Mathematics.
2+ years of experience in layout of multi layer MLO/RDL and ceramic substrates.
Basic understanding of package design processes.
Good understanding of impedance control, return paths, and inductance loops, with hands on experience working on multi layer stackups with core and coreless packages.
Exposure to signal integrity (SI) and power integrity (PI) preferred, along with routing experience with SI and PI aware design of SERDES, DDR, and HSIO (Gen3/4/5/6).
Awareness of manufacturing processes and materials used in advanced packaging, plus familiarity with Cadence tools.
Self motivated with strong analytical thinking, and able to work well in teams across multiple disciplines such as thermal, mechanical, electrical, reliability, and component functions.