SoC - Physical Implementation, Staff Engineer
Ho Chi Minh - VN, Muscat - OM & Hsinchu - TW
Full Time
Position Overview
The SOC – Physical Implementation Staff Engineer is responsible for owning and executing a part of RTL to GDSII tasks for complex SoC/ASIC blocks or medium scale partitions. This role takes responsibility for constraint quality, synthesis flow, timing closure planning, and cross team technical alignment within assigned domains. The Staff Engineer independently drives problem resolution, improves flow robustness, and supports junior engineers through technical guidance. This role offers the opportunity to work on cutting edge silicon in a fast growing US semiconductor company and contribute to high impact SoC programs.
Key Responsibilities
Perform and own RTL‑to‑implementation quality checks (LDRC, VCLP, GCA, LEC) for assigned blocks; proactively drive issue resolution with RTL, DFT and PD teams.
Create and refine SDC constraints for complex blocks; ensure consistency, correctness, and alignment with full-chip timing intent.
Run synthesis flows (logical + physical), analyze QoR, and implement optimizations to meet timing, area, and power targets for assigned partitions.
Perform in Static Timing Analysis (STA) across modes and corners, including setup/hold analysis, SI/crosstalk impact, noise-related timing effects, timing closure support, and timing ECO generation for assigned blocks or modules.
Conduct power analysis and support low-power implementation checks to improve power quality and identify potential issues early in the design flow.
Collaborate closely with Physical Design engineers, especially during placement and Clock Tree Synthesis (CTS), to align constraints, timing intent, QoR targets, and implementation feedback for assigned blocks or modules.
Collaborate closely with DFT engineers for DFT insertion flow in synthesis and PnR stage.
Contribute to methodology improvement, flow automation, checklist development, and best-practice sharing for SoC Physical Implementation projects.
Provide informal mentorship to junior engineers; review reports, help debug issues, and share best practices
Participate in technical discussions with customer teams; provide clear updates and support issue resolution within assigned scope.
Qualifications
6–9 years of experience in ASIC/SoC Physical Implementation, synthesis, STA, or RTL‑to‑GDSII flows.
Strong hands-on experience owning block-level or medium-scale partition implementation tasks.
Deep knowledge of SDC constraints, synthesis flows, STA, timing closure, and ECO methodologies.
Proficiency with industry-standard tools: Synopsys DC/FC, PrimeTime, Cadence Genus/Tempus, or equivalent.
Experience with hand-off quality checks (LDRC, VCLP, GCA, LEC) and ability to debug issues independently.
Solid understanding of power analysis and low-power design concepts.
Good knowledge of ASIC/SoC methodology, hierarchical flows, and PPA trade-offs.
Strong scripting skills (TCL, Python, Perl) for automation and debug.
Strong analytical, debugging, and communication skills; ability to work effectively with global teams.