SOC - Physical Implementation, Sr Staff Engineer
Ho Chi Minh - VN, Muscat - OM & Hsinchu - TW
Full Time
Position Overview
The SOC – Physical Implementation Senior Staff Engineer serves as a technical expert for a part of RTL to GDSII execution across major SoC/ASIC partitions or multi-block domains. This role drives constraint strategy, synthesis methodology, timing convergence planning, and power/performance optimization at a scale beyond individual blocks. The Senior Staff Engineer leads cross-functional technical alignment, resolves complex design issues, and influences methodology and flow improvements across project. This role offers the opportunity to work on cutting edge silicon in a fast growing US semiconductor company and contribute to high impact SoC programs.
Key Responsibilities
Oversee RTL‑to‑implementation quality checks (LDRC, VCLP, GCA, LEC) across multiple blocks or partitions; drive systemic issue resolution with RTL, PD, and DFT teams.
Architect SDC constraints for large partitions or hierarchical domains; ensure consistency across blocks and alignment with full-chip timing intent.
Define synthesis strategies (logical + physical), guide QoR improvements, and make PPA trade-off decisions impacting multiple blocks or subsystems.
Lead multi-corner STA, SI/crosstalk analysis, noise evaluation, and timing ECO strategy for large partitions; collaborate with full-chip timing teams to ensure convergence.
Drive power analysis across multiple blocks, identify systemic inefficiencies, and influence low-power design and implementation strategies.
Coordinate with Physical Design, RTL, DFT, and Verification teams to ensure constraints, timing intent, and QoR targets are aligned across partitions.
Collaborate closely with DFT engineers for DFT insertion flow in synthesis and PnR stage. Ensure timing, area, and power impacts are well-managed across multiple blocks.
Lead development of automation, checklists, and best practices; influence team-wide or project-wide methodology improvements.
Mentor Staff and Senior engineers, review complex reports, provide guidance on synthesis, STA, constraints, and ECO flows.
Lead technical discussions with customer teams, present design status, and drive resolution of complex issues in global project environments.
Qualifications
9+ years of experience in ASIC/SoC Physical Implementation, synthesis, STA, or RTL‑to‑GDSII flows.
Proven ownership of large partitions, multi-block domains, or hierarchical implementation scopes.
Deep expertise in SDC constraint architecture, synthesis methodology, STA, timing closure, and ECO strategies.
Strong proficiency with industry-standard tools: Synopsys DC/FC, PrimeTime, Cadence Genus/Tempus, or equivalent.
Extensive experience with hand-off quality checks (LDRC, VCLP, GCA, LEC) and ability to drive cross-team resolution.
Strong understanding of power analysis, low-power design techniques, and power-aware implementation flows.
Broad knowledge of full-chip methodology, hierarchical flows, PPA trade-offs, and cross-functional dependencies.
Advanced scripting skills (TCL, Python, Perl) for automation, debug, and methodology development.
Excellent communication, leadership, and problem-solving skills; ability to lead technical discussions with global teams and customers.