SoC - Physical Design, Sr Staff Engineer
Ho Chi Minh - VN, Hsinchu - TW & Muscat - OM
Full Time
Position Overview
The SOC Physical Design Senior Staff Engineer is a technical authority for PnR, EMIR, PV, and timing convergence across major SoC partitions or multi-block domains. This role shapes PD methodology, drives cross-team alignment, resolves complex signoff issues, and leads technical execution for large-scale implementation efforts. This role offers the opportunity to work on cutting edge silicon in a fast growing US semiconductor company and contribute to high impact SoC programs.
Key Responsibilities
Lead PnR strategies for large partitions or subsystems.
Drive multi-corner timing closure, SI/crosstalk mitigation, ECO strategy across domains.
Define EMIR methodology, identify systemic issues, and drive closure across multiple blocks.
Lead PV strategy for large partitions
Resolve complex DRC/LVS issues
Guide PV methodology and signoff criteria
Ensure PV consistency across hierarchical designs
Define best practices, improve automation, influence project-wide PD methodology.
Align PD, STA, RTL, DFT, and full-chip teams on constraints, timing intent, and signoff strategy.
Mentor Staff/Senior engineers; review complex reports and guide debugging.
Lead technical discussions with customer teams; drive resolution of high-impact issues.
Qualifications
9+ years of experience in Physical Design with ownership of multi-block domains or major SoC partitions.
Expert-level knowledge of hierarchical PnR, including partitioning strategy, floorplan architecture, and cross-block optimization.
Advanced proficiency in timing convergence, multi-corner/multi-mode STA, SI/crosstalk mitigation, and ECO strategy across domains.
Deep expertise in EMIR methodology, systemic IR/EM issue identification, and signoff closure across multiple blocks.
Strong authority in PV signoff, including resolving complex DRC/LVS issues, defining PV methodology, and ensuring hierarchical PV consistency.
Broad understanding of full-chip flows, PPA trade-offs, physical architecture, and cross-functional design dependencies.
Experience influencing methodology, automation, and best practices across teams or projects.
Strong leadership in cross-functional technical alignment (RTL, STA, DFT, PD, full-chip).
Ability to mentor Staff/Senior engineers and guide complex debug efforts.
Excellent communication and customer-facing technical leadership skills.